--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:47:46 10/03/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207_TEST/LAB2/test_32x32_mult.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Unsigned_32x32_mult
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test_32x32_mult IS
END test_32x32_mult;
 
ARCHITECTURE behavior OF test_32x32_mult IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Unsigned_32x32_mult
    PORT(
         clk : IN  std_logic;
         arg1 : IN  std_logic_vector(31 downto 0);
         arg2 : IN  std_logic_vector(31 downto 0);
         start_signal : IN  std_logic;
         result : OUT  std_logic_vector(63 downto 0);
			is_signed : IN std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal arg1 : std_logic_vector(31 downto 0) := (others => '0');
   signal arg2 : std_logic_vector(31 downto 0) := (others => '0');
   signal start_signal : std_logic := '0';
	signal is_signed : STD_LOGIC := '0';

 	--Outputs
   signal result : std_logic_vector(63 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Unsigned_32x32_mult PORT MAP (
          clk => clk,
          arg1 => arg1,
          arg2 => arg2,
          start_signal => start_signal,
          result => result,
			 is_signed => is_signed
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;
		
		---- UNSIGNED---
		is_signed <= '0';
		-- TEST 1a: 3h * 5h = 15 = 0Fh --
		start_signal <= '1';
		arg1 <= x"00000003";
		arg2 <= x"00000005";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 1b: 11111111h * FFFFFFFFh = 11111110EEEEEEEFh
		start_signal <= '1';
		arg1 <= x"11111111";
		arg2 <= x"FFFFFFFF";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;

		-- TEST 1c: 12345678h * 87654321h = 09A0CD0570B88D78h
		start_signal <= '1';
		arg1 <= x"12345678";
		arg2 <= x"87654321";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;

		-- TEST 1d: FFFFFFFFh * FFFFFFFFh = FFFFFFFE00000001h
		-- Test if carry is handled correctly
		start_signal <= '1';
		arg1 <= x"FFFFFFFF";
		arg2 <= x"FFFFFFFF";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 1e: 0h * 0h = 0h
		start_signal <= '1';
		arg1 <= x"00000000";
		arg2 <= x"00000000";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		------------------
		-- Random Tests --
		------------------
		-- TEST 2a: 0FEABEAFh * 54321234h = 053C238C6745098Ch
		start_signal <= '1';
		arg1 <= x"0FEABEAF";
		arg2 <= x"54321234";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 2b: 12345678h * 12121212h = 148F70B7A328470h
		start_signal <= '1';
		arg1 <= x"12345678";
		arg2 <= x"12121212";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		--------------------------------
		-- signed
		--------------------------------
		is_signed <= '1';
		-- TEST 3a : -3 * -5 = FFFFFFFDh * FFFFFFFBh = 00...fh
		start_signal <= '1';
		arg1 <= x"FFFFFFFD";
		arg2 <= x"FFFFFFFB";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 3b : -3 * 5 = FFFFFFFDh * 5h = fff....1h
		start_signal <= '1';
		arg1 <= x"FFFFFFFD";
		arg2 <= x"00000005";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 3c : -5 * 3 = FFFFFFFBh * 3h = ff....1h
		start_signal <= '1';
		arg1 <= x"FFFFFFFB";
		arg2 <= x"00000003";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 3d : 8ABCDEFAh * 19ABCDEFh = -1967333638d * 430689775d = F43DBF9B1FE05D66h
		start_signal <= '1';
		arg1 <= x"8ABCDEFA";
		arg2 <= x"19ABCDEF";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 3e : -2h * 0h = FFFFFFFEh * 0h = 0h
		start_signal <= '1';
		arg1 <= x"FFFFFFFE";
		arg2 <= x"00000000";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		-- TEST 3f : 0h * -2h = 0h * FFFFFFFEh = 0h
		start_signal <= '1';
		arg1 <= x"00000000";
		arg2 <= x"FFFFFFFE";
		wait for clk_period * 1;
		start_signal <= '0';
		wait for clk_period * 5;
		
		
      wait;
   end process;

END;
